Using Address Apertures - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
Release Date
2023.2 English

Each BDC has an addressable space available for connecting masters and slaves. The DFX BDC boundary apertures can either be manually specified, or left onto IP integrator to automatically infer them.

Tip: For DFX designs, the Manual setting is advised.
Apertures will be automatically inferred by looking at all the design sources in the BDC. If an RM has apertures specified manually on the boundary, these will be used to compute the BDC apertures for the container. If not, boundary assignments in the child will be used for calculations. This will occur regardless of whether a bottom-up or top-down approach is used.

If your static design has already been implemented with certain auto-computed apertures, adding a new RM source to the BDC will cause IP integrator to re-compute those apertures. If the calculated apertures are different than the previously computed apertures, the static result will be marked out of date and will need to be re-implemented.

Apertures (either manually specified or derived from address assignments in the child) in the child will be validated against the manually specified apertures. If they are not compatible, DRCs will be issued.

Any new RM created using the Create Reconfigurable Module command for a BDC will inherit the BDC-specified apertures. This is more relevant to the top-down flow.

Save Block Design As has been enhanced to Freeze the boundary of the new BD, which copies apertures from the current BD (presumably the default RM source), along with rest of the boundary and freeze it. In bottom-up flows, it ensures that newly created RMs are always restricted to match the BDC boundary.

Figure 1. Viewing the Address Aperture for a BDC

Always use manual apertures for DFX designs to ensure that all the RM addressing fits within the top block design address space. If manual apertures are not used for a DFX design, the Vivado tools report a warning.

You can validate block designs using validate_bd_design -assign_dfx_addressing. The assign_dfx_addressing switch is an optional value used to consolidate addressing across RMs in DFX blocks. This argument makes every RM active in the context of the top and reassigns addressing to make the RM fit into the top. Manual apertures guide the flag on how to change the RM addresses.

Aperture overlaps on interfaces passing though the same network are not allowed, because SmartConnect and NoC instances connected to these interfaces would fail to elaborate. IP integrator overlapping errors can occur when using Auto apertures for multiple RP designs in which the Vivado tools need to adjust the addressing to meet a power of 2 and minimum 64K requirement.

Avoid DFX BDCs that use only a single routing bridge IP (such as a SmartConnect or NoC IP), which is also known as a pass-through RM. The change in routing that can occur when switching RMs between a static master and static slave both at the top level of the design is not supported, because it requires the master to know how to communicate with a slave at potentially two different addresses. A DRC occurs when an RM contains only a pass-through bridge IP. For example:

[BD 41-2913] The assignment from address space '/versal_cips_0/FPD_CCI_NOC_0' at '0x201_0000_0000 [ 64K ]' to slave segment '/axi_gpio_0/S_AXI/Reg' passes through a BDC with routing bridge IP '/rp1/axi_gpio_0_smc'. This path is highly discouraged since changing the BDC variant can cause routing of two different assignments between the same static address space and static slave, which is not supported by most routing bridge IPs. Please consider modifying the design to avoid using BDCs which contain only routing bridge IPs.