NoC Clock Gating Issue - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
Release Date
2023.2 English
Versal devices have a clock gating capability within the NoC to reduce power consumption due to unused clock buffers. This feature is not yet supported for certain DFX use cases.
  • For DFX designs that contain a single RP that contains NoC resources, the feature is supported and it is ON by default.
  • For DFX designs that contain two or more RP that contain NoC resources, this feature is automatically disabled.
  • For DFX designs that target devices that use stacked silicon interconnect (SSI) technology, the feature is automatically disabled.
Figure 1. NoC Clock Gating Summary

When this feature is disabled, the partial PDI can function properly, but the ungated clock buffers consumes 37 mW per buffer, and this additional power needs to be accounted for in Vcc_SoC rail and power supply design. When calculating power consumption within the Power Design Manager, be sure to set the DFX operating conditions to match your use case for the most accurate results.

Figure 2. NoC Clock DFX