Multi-SLR Dynamic Regions - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

When creating Reconfigurable Partitions that span multiple SLR, it is recommended to include a full clock region above and below the SLR boundary to capture as many super long lines (SLL) within the width of the RP as possible. These SLLs are the routing resources crossing the SLR boundary, and by allowing a full clock region above and below, you improve the routability for that RP. If high-performance modules have difficulty closing timing, consider placing these modules within their own Pblock within the reconfigurable Pblock to ensure the logic is not spread across multiple SLRs.