Known Limitations - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
Release Date
2023.2 English

Certain features are not yet developed or supported in the current release. These include:

  • When selecting Pblock ranges to define the size and shape of the RP, do not use the CLOCKREGION resource type for 7 series or Zynq 7000 designs. Pblock ranges must only include types SLICE, RAMB18, RAMB36, and DSP48 resource types.
  • Do not use Vivado Debug core insertion features within RPs when working with 7 series, UltraScale, or UltraScale+ devices. This flow inserts the debug hub, which includes BSCAN primitive, which is not permitted inside reconfigurable bitstreams. Vivado Debug cores must be instantiated or included within IP for these architectures, then the Debug Hub can be inferred as described in Using Vivado Debug Cores.
  • The Soft Error Mitigation (SEM) IP core is supported with DFX in monolithic devices. For UltraScale devices, the SEM IP core is not supported when using Dynamic Function eXchange on SSI devices. For UltraScale+ devices, the SEM IP core is supported when using DFX on SSI devices. For more information on using the SEM IP in DFX designs, see Demonstration of Soft Error Mitigation IP and Partial Reconfiguration Capability on Monolithic Devices (XAPP1261).
  • The STARTUP primitive does not support loading of partial bitstreams for 7 series and UltraScale devices, because its clock will stop after a partial bitstream enters the configuration engine. IP, such as the AXI SPI IP or the AXI EMC IP, should not be configured to use the STARTUP primitive to clock or deliver partial bitstreams from external flash. For these architectures, partial bitstreams may be stored in BPI or SPI flash, but they must be moved to DDR memory or another location before being shifted into the ICAP.
  • Two use cases regarding encryption will not be supported when using new features within UltraScale and UltraScale+ devices:
    1. If RSA authentication is selected for the initial configuration, then encrypted partial reconfiguration is not supported. RSA authentication is not supported on FPGAs for partial bitstreams.
    2. If the initial configuration bitstream uses an obfuscated AES-256 key stored in either the eFUSE or BBRAM, then any encrypted partial bitstreams must use the same obfuscated key. Encrypted partial bitstreams using a different key than the initial bitstream is not supported.

      In either of these two cases, an unencrypted partial bitstream can be delivered to the ICAP to partially reconfigure the device.

  • Bitstream compression and per-frame CRC checks cannot be enabled at the same time for a partial bitstream for 7 series, UltraScale, or UltraScale+ devices.
  • The update_design command in general permits multiple targets for the -cells switch. However, when using this command for DFX designs (for use with -black_box or -buffer_ports), specify one cell (RP) at a time. Performing these actions on more than RP requires multiple calls to update_design.
  • Cascaded global clocking buffers across RM boundary is not a supported use case and is not guaranteed to be successfully routed. If cascaded BUFS are unavoidable in the design, it is recommended to keep them both, either in static or RP.
  • All RP ports must be strictly input or output in direction. Ports of type inout are not supported. Partition pins are established on boundary ports by selecting routing points or resource pins that are strictly unidirectional, so changing the direction at these points is physically impossible.