Floorplan in the Vivado IDE - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

The Vivado IDE can be used for planning and visualization tasks. The best example of this is using the Device view to create and modify Pblock constraints for floorplanning.

  1. Open the synthesized static design and the largest of each RM. Here are the commands, using the tutorial design (found in the Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947) as an example:
    open_checkpoint synth/Static/top_synth.dcp
    set_property HD.RECONFIGURABLE true [get_cells inst_count]
    read_checkpoint -cell [get_cells inst_count] synth/count_up/count_synth.dcp
    set_property HD.RECONFIGURABLE true [get_cells inst_shift]
    read_checkpoint -cell [get_cells inst_shift] synth/shift_right/shift_synth.dcp

    At this point, a full configuration has been loaded into memory, and the RPs have been defined.

  2. To create Pblock constraints for the RPs, right-click on an instance in the Netlist window (in this case, inst_count or inst_shift) and select Draw Pblock. Create a rectangle in the Device view to select resources for this RP.
  3. With this Pblock selected, note that the Pblock Properties pane shows the number of available and required resources. The number required is based on the currently loaded RM, so keep in mind that other modules may have different requirements. If additional rectangles are required to build the appropriate shape (an "L", for example), right-click the Pblock in the Device view and select Add Pblock Rectangle.
  4. Design rule checks (DRCs) can be issued to validate the floorplan and other design considerations for the in-memory configuration. To run, select Reports > Report DRC and ensure the DFX checks are present (see Floorplan in the Vivado IDE). Note that if HD.RECONFIGURABLE has not been set on a Pblock, only a single DRC is available, instead of the full complement shown below.

This set of DRCs can be run from the Tcl Console or within a script, by using the report_drc command. To limit the checks to the ones shown here for DFX, use this syntax:

report_drc -checks [get_drc_checks HDPR*]

To extend the DRCs to those checked during specific phases of design processing the -ruledeck option can be used. For example, the following command can be issued on a placed and routed design:

report_drc -ruledeck bitstream_checks 

To save these floorplanning constraints, enter the following command in the Tcl Console:

write_xdc top_fplan.xdc

The Pblock constraints stored in this constraints file can be used directly or can be copied to another top-level design constraints file. This XDC file contains all the constraints in the current design in memory not just the constraints recently added.

Do NOT save the overall design from the Vivado IDE using File > Checkpoint > Save or the equivalent button. If you save the currently loaded design in this way, you will overwrite your synthesized static design checkpoint with a new version that includes RMs and additional constraints.