Dynamically Reconfigurable Packet Processor - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

A packet processor can use Dynamic Function eXchange to change its processing functions quickly, based on the packet types received. In Dynamically Reconfigurable Packet Processor, a packet has a header that contains the partial BIT file, or a special packet contains the partial BIT file. After the partial BIT file is processed, it is used to reconfigure a co-processor in the FPGA. This is an example of the FPGA reconfiguring itself based on the data packet received instead of relying on a predefined library of partial BIT files.

Figure 1. Dynamically Reconfigurable Packet Processor
Page-1 Sheet.1 FPGA FPGA Sheet.2 ICAP ICAP Sheet.3 Packet Processor Packet Processor Sheet.4 Partially Reconfigurable Co-processor PartiallyReconfigurableCo-processor Sheet.5 Data Data Sheet.6 Data Data Sheet.7 PBF PBF Sheet.8 H H Sheet.9 Data Data Sheet.10 PBF PBF Sheet.11 H H Sheet.12 PBF: Partial Bit File PBF: Partial Bit File Sheet.13 1 1 Sheet.14 2 2 Standard Arrow.483 Standard Arrow.16 Sheet.17 Standard Arrow.494 Sheet.19 Sheet.20 Sheet.21 2 2 Sheet.22 1 1 Graphic ID: HW - Fig# only X12005 X12005