Creating Reconfigurable Partition Pblocks Manually - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

If automatic modification to the RP Pblock is not desired to fix back-to-back issues, you can create Pblock ranges manually to meet your needs. This is most useful when explicit control is needed for Pblocks that must span non-reconfigurable sites, such as configuration blocks or the center column, which contains clock buffer resources.

In Creating Reconfigurable Partition Pblocks Manually, note that the left and right edges are drawn between CLB columns for the Pblock highlighted in white. Visualization of the interconnect tiles as shown in this image requires that the routing resources are turned on, using this symbol in the Device View .

Figure 1. Optimal - Reconfigurable Partition Pblock Splitting CLB-CLB on Both Left and Right Edges

The RP Pblock must include all reconfigurable element types within the shape drawn. In other words, if the rectangle selected encompasses CLB (Slice), block RAM, and DSP elements, all three types must be included in the Pblock constraints. If one of these is omitted, a DRC is triggered with an alert that a split interconnect situation has been detected.

Other considerations must be taken if the RP spans non-reconfigurable sites, such as the center-column clocking resources or configuration components (ICAP, BSCAN, etc.), or abuts non-reconfigurable components such as I/O. If a Pblock edge splits interconnect columns for different resource types, implementation tools accept this layout, but restrict placement in the columns on each side of the boundary. If this prohibits sites that are needed for the design (such as the ICAP or BSCAN, for example), the Pblock must be broken into multiple rectangles to clearly define reconfigurable logic usage, or SNAPPING_MODE must be used.

The implementation tools automatically prevent placement on both sides of the back-to-back interconnect by creating PROHIBIT constraints. If the sites that are prohibited due to a back-to-back violation are not needed in the design, it is acceptable to leave the back-to-back violation in the design. Doing so allows an extra column of routing tiles to be included in the dynamic region, and can reduce congestion in a dynamic region that spans non-reconfigurable sites. In this case, a Critical Warning is issued by DRCs, but the warning can be safely ignored if you understand the trade-offs of placement versus routing resources.

The one exception to this behavior is around the clock column. If a violation occurs at the clock column boundary, PROHIBIT constraints are generated for the RM side of the violation (typically SLICE prohibits), but the clocking resources do not get prohibit constraints and are still available to the static logic. The SNAPPING_MODE property has a value of ROUTING, which takes advantage of this special exception. For example, the initial floorplan shown in Creating Reconfigurable Partition Pblocks Manually spans the center column, which contains clock buffer resources (BUFHCE/BUFGCTRL). These resources have not been included in the Pblock, as they are not highlighted in Creating Reconfigurable Partition Pblocks Manually. There is violation caused by spanning this clock column but the resources can still be used by the static logic.

Figure 2. Pblock Spanning Non-Reconfigurable Sites

Prohibited sites appear in placed or routed checkpoints as sites with a red circle with a slash, as shown in Creating Reconfigurable Partition Pblocks Manually. With this automatic prohibit feature, the routing interconnect associated with reconfigurable sites (CLBs) can still be used for the RM even though the CLBs themselves are not used. In Creating Reconfigurable Partition Pblocks Manually, the column of INT on the left is available for the RM, but the column of INT on the right is only available for static logic because these are part of the clock tile, which is not reconfigurable for 7 series devices.

Figure 3. Prohibited Sites in a Checkpoint

If a back-to-back violation prohibits sites that are needed for the design (that is, ICAP or BSCAN sites), a placement error is issued, stating that not enough sites are available in the device.

ERROR: [Common 17-69] Command failed: Placer could not place all instances

To avoid this restriction, create multiple Pblock rectangles that avoid splitting interconnect columns, as shown in Creating Reconfigurable Partition Pblocks Manually, or use the Pblock SNAPPING_MODE property.

In general, spanning non-reconfigurable site types (such as IOB, configuration, or clocking columns) should be avoided whenever possible. If the Pblock must span one of these, the clocking column is the least risky choice, owing to its special nature (described previously). Use SNAPPING_MODE ROUTING to cross this boundary as efficiently as possible.

Figure 4. Multiple Pblock Rectangles that Avoid Non-Reconfigurable Resources

Creating Reconfigurable Partition Pblocks Manually is a close-up of this split, showing Slice (CLB) and Interconnect (INT) resource types. The gap between the two Pblock rectangles gives full access to the BUFHCE components to route completely using static resources. This also leaves one column of CLBs available for the static design to use. Although routing resources exist that can cross these gaps, the overall routability of such structures is notably reduced. This approach is more challenging and should be avoided if possible. When spanning other static boundaries, such as IOB or configuration tiles, the routing gap for the dynamic region becomes two INT resources, and routing becomes difficult.

Figure 5. Close-up Showing Columns Reserved for Clock Routing Usage

Irregular shaped Partitions (such as a T or L shapes) are permitted, but you are encouraged to keep overall shapes a simple as possible. Placement and routing in such regions can become challenging because routing resources must be entirely contained within these regions. Boundaries of Partitions can touch, but this is not recommended, as some separation helps mitigate potential routing restriction issues. Nested or overlapping RPs (partitions within partitions) are not permitted.

Finally, only one RP can exist per physical Reconfigurable Frame. A Reconfigurable Frame is the smallest size physical region that can be reconfigured, and aligns with clock region boundaries. A Reconfigurable Frame cannot contain logic from more than one RP. If it were to contain logic from more than one RP, it would be very easy to reconfigure the region with information from an incorrect RM, thus creating contention. The Vivado tools are designed to avoid that potentially dangerous occurrence.