Creating Pblocks for 7 Series Devices - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

As noted in Apply Reset After Reconfiguration, the height of the RP must align to clock region boundaries if RESET_AFTER_RECONFIG is to be used. Otherwise, any height can be selected for the RP.

The width of the RP must be set appropriately to make most efficient usage of interconnect and clocking resources. The left and right edges of Pblock rectangles should be placed between two resource columns (for example, CLB-CLB, CLB-block RAM or CLB-DSP) and not between two interconnect columns (INT-INT). This allows the placer and router tools the full use of all resources for both static and reconfigurable logic. Implementation tool DRCs provide guidance if this approach is not followed.