Configuration by Means of Standard Bus Interface - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

Dynamic Function eXchange can create a new configuration port using an interface standard more compatible with the system architecture. For example, the FPGA could be a peripheral on a PCIe® bus and the system host could configure the FPGA through the PCIe connection. After power-on reset the FPGA must be configured with a full BIT file. However, the full BIT file might only contain the PCIe interface and connection to the internal configuration access port (ICAP).

Bitstream compression can be used to reduce the size and therefore configuration time of this initial device load, helping the FPGA configuration meet PCIe enumeration specifications.

The system host could then configure the majority of the FPGA functionality with a partial BIT file downloaded through the PCIe port as shown in Configuration by Means of Standard Bus Interface. An example of fast configuration over PCIe is shown in Fast Partial Reconfiguration Over PCI Express Application Note (XAPP1338), with an example targeting AMD UltraScale+™ included.

Figure 1. Configuration by Means of PCIe Interface

The PCIe standard requires the peripheral (the FPGA in this case) to acknowledge any requests even if it cannot service the request. Reconfiguring the entire FPGA would violate this requirement. Because the PCIe interface is part of the static logic, it is always active during the dynamic reconfiguration process, thus ensuring that the FPGA can respond to PCIe commands even during reconfiguration.

Tandem Configuration is a related solution that at first glance appears to be the same as is shown here. However, the solution using Dynamic Function eXchange differs from Tandem Configuration in two regards:

  • The configuration process with DFX is a full device configuration, made smaller and faster through compression, followed by a partial bitstream that overwrites the black box region to complete the overall configuration. Tandem Configuration is a two-stage configuration where each configuration frame is programmed exactly once.
  • Tandem Configuration for 7 series devices does not permit dynamic reconfiguration of the user application. Using DFX, the dynamic region can be reloaded with different user applications or field updates. Tandem Configuration for UltraScale and UltraScale+ devices does permit Field Updates and compatibility with DFX in general. The overall flow is Tandem Configuration for a two-stage initial load, followed by partial reconfiguration to dynamically modify the user application.

Tandem Configuration is designed to be a specific solution for a specific goal: fast configuration of a PCIe endpoint to meet enumeration requirements. For more information, see the following manuals:

  • 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
  • Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
  • UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
  • UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)