Configuration Frames - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

All user-programmable features inside AMD FPGA and SoC devices are controlled by volatile memory cells that must be configured at power-up. These memory cells are collectively known as configuration memory. They define the LUT equations, signal routing, IOB voltage standards, and all other aspects of the design.

AMD FPGA and SoC architectures have configuration memory arranged in frames that are tiled about the device. These frames are the smallest addressable segments of the device configuration memory space, and all operations must therefore act upon whole configuration frames.

Reconfigurable Frames are built upon these configuration frames, and these are the minimum building blocks for performing dynamic reconfiguration. All dimensions based on the fundamental element described.

  • Base Regions in 7 series FPGAs are a full clock region high:
    50 high by 1 wide
    10 high by 1 wide
    Block RAM
    10 high by 1 wide

The granularity of global signals (GSR) in 7 series is at the clock region level, so full columns of elements are initialized upon reconfiguration. Even if RESET_AFTER_RECONFIGURATION is not used, partial bitstream composition is based on clock region high columns.

  • Base Regions in UltraScale and UltraScale+ FPGAs are a full clock region high:
    60 high by 1 wide
    24 high by 1 wide
    Block RAM
    12 high by 1 wide
    I/O and Clocking
    52 I/O (one bank), plus related XiPhy, MMCM, and PLL resources
    Gigabit Transceivers
    Four high (one quad, plus related clocking resources)

The granularity of global signals (GSR) in UltraScale and UltraScale+ is at the element level, so individual elements are initialized upon reconfiguration, and RESET_AFTER_RECONFIGURATION is not needed. However, partial bitstream composition is still based on clock region high columns, and any static logic elements in these regions are NOT initialized after reconfiguration even though they are contained within the partial bitstream.