Configuration Debugging - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

The ICAP interface can be use used to monitor the configuration process when it is used as the port for delivering bitstreams. The "O" port of the ICAP block is a 32-bit bus, but only the lowest byte is used. The mapping of the lower byte is as follows:

Table 1. ICAP “O” Port Bits
ICAP “O” Port Bits Status Bit Meaning

Configuration error (active-Low)

0 = A configuration error has occurred.

1 = No configuration error.


Sync word received (active-High)

0 = No sync word received.

1 = Sync word received by interface logic.

O[5] RIP

Readback in progress (active-High)

0 = No readback in progress.

1 = A readback is in progress.


ABORT in progress (active-Low)

0 = Abort is in progress.

1 = No abort in progress.

O[3:0] 1 Reserved

The most significant nibble of this byte reports the status. These Status bits indicate whether the Sync word been received and whether a configuration error has occurred. The following table displays the values for these conditions.

Table 2. ICAP Sync Bits
O[7:4] Sync Word? CFGERR?
9 No Sync No CFGERR
1 No Sync CFGERR
Note: In the above table, the entries in the first column are different depending on the board. For 7 series devices, they end with “F”, so 9F, DF, etc. For UltraScale+ devices, they end with “B”, so 9B, DB, etc.

Configuration Debugging shows a completed full configuration, followed by a partial reconfiguration with a CRC error, and finally a successful partial reconfiguration. Using the table above, and the description below, you can see how the “O” port of the ICAP can be used to monitor the configuration process. If a CRC error occurs, these signals can be used by a configuration state machine to recover from the error. These signals can also be used by Vivado Logic Analyzer to capture a configuration failure for debug purposes. With this information Vivado Logic Analyzer can also be used to capture the various points of a partial reconfiguration.

Figure 1. Vivado Logic Analyzer Display for Dynamic Function eXchange

The markers in the Vivado Logic Analyzer display indicate the following:

This marker indicates the completion of the initial full bitstream configuration. The DONE pin (done_pad in this waveform) goes HIGH.
This marker indicates a CRC error is detected while loading partial bitstream. The status can be observed through O[31:0] (icap_o_top[31:0] in the waveform).
  • Icap_o_top[31:0] starts at 0x9F
  • After seen SYNC word, Icap_o_top[31:0] change to 0xDF
  • After detect CRC error, Icap_o_top[31:0] change to 0x5F for one cycle, and then switches to 0x1F
  • INIT_B pin is pulled Low (init_pad in the waveform)
This marker indicates when the partial bitstream is loaded again. The RCRC command resets the cfgerr status, and removes the pull-down on the INIT_B pin (init_pad in this waveform).
  • Icap_o_top[31:0] change from 0x1F to 0x5F when the SYNC word is seen
  • Icap_o_top[31:0] change from 0x5F to 0xDF when RCRC command is received
This marker indicates a successful partial reconfiguration.
  • Icap_o_top[31:0] change from 0xDF to 0x9F when the DESYNC command is received and no configuration error is detected.

In addition to the techniques described above, the UltraScale architecture introduced two new dedicated ports on the ICAP to aid in Dynamic Function eXchange:

  • The PRDONE pin is intended to echo the external DONE pin. However, it should only be used for the following:
    • Monolithic devices
    • SSI devices when the RP is on the master SLR
    • When the ICAP used is on the same SLR as the RP.

    Any partial bitstream that configures a slave SLR from the master ICAP will see multiple PRDONE events due to the construction of these partial bitstreams. Instead, use the EOS pin on the STARTUP block on the master SLR (or on the target SLR if the RP is not on the master SLR) as a reliable indication of the completion of partial reconfiguration.

  • The PRERROR pin echoes the external INIT_B pin. It drops LOW when a CRC error occurs, either with the standard full CRC value at the end of the bit file, or with any per-frame CRC value. The value will reset after each segment of the partial bitstream so the failure pulse must be captured by the user design.

For more information on configuration behavior, see the UltraScale Architecture Configuration User Guide (UG570).