Bitstream Creation - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

The Nested DFX design methodology moves the HD.RECONFIGURABLE property down and up through the hierarchy. Implementation tools follow standard DFX design rules based on what cells are currently defined as reconfigurable. This holds true for write_bitstream as well; partial bitstreams will only be created for cells currently holding the HD.RECONFIGURABLE property.

With any fully routed design checkpoint open in Vivado, use write_bitstream to generate full and partial bitstreams. Remember, by default this command will generate a standard full bitstream for the entire device and a partial bitstream for each cell defined as reconfigurable. Two options can limit results to one or the other:

  1. The -cell option will generate ONLY a partial bitstream for the requested cell.
  2. The -no_partial_bitfile option will generate ONLY a standard full device bitstream.

If the full design image you need a full device bitstream for, use a combination of open_checkpoint and read_checkpoint -cell (and update_design -black_box if necessary) to assemble a complete routed design, filling in each module one at a time with routed RM checkpoints. Use report_route_status to confirm that the design is complete.

Figure 1. Assembled Design for Bitstream Generation

For example, to create all bitstreams possible for the above design configuration, follow these steps. These commands assume that checkpoints for each module alone (each routed, and some locked) have been created using the same naming conventions as the A1 variants.

open_checkpoint top_A2_Y1_Z1_routed.dcp
update_design -black_box -cell A/Y
read_checkpoint -cell A/Y Y2_routed.dcp
write_bitstream top_A2_Y2_Z1.bit

This last command will create three bitstreams:

  1. top_A2_Y2_Z1.bit, which is the full design bitstream for the entire device
  2. top_A2_Y2_Z1_pblock_Y_partial.bit, which is the partial bitstream for Y2 only
  3. top_A2_Y2_Z1_pblock_Z_partial.bit, which is the partial bitstream for Z1 only

Note that the names for the partial bitstreams are automatically generated. The name always starts with the base name you provided, followed by the RP pblock name, followed by partial. If you would like to have names that show the name of the current RM (for example Y2), then call write_bitstream on the target RP directly:

write_bitstream -cell A/Y top_A2_Y2_partial.bit
write_bitstream -cell A/Z top_A2_Z1_partial.bit

Partial bitstreams can only be generated for cells currently marked as HD.RECONFIGURABLE. In order to create a partial bitstream for RP A, pr_recombine must be called before write_bitstream.

pr_recombine -cell A
write_bitstream -cell A A2_Y2_Z1_partial.bit

A full device bitstream for this image would be identical to one generated prior to pr_recombine, as the full device bitstream does not have any special programming indicating that later that device will be partially reconfigured.