Avoid Disjoint Pblocks Whenever Possible for UltraScale and UltraScale+ Devices - 2023.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2023.2 English

AMD highly recommends contiguous floorplanning for static regions and reconfigurable Pblocks for many reasons, including the following:

  • Disjoint Pblocks for either a reconfigurable partition or the static region can result in related logic being placed in separate areas, which will have a negative impact on routability and timing closure. Without additional guidance, it is possible for the placer to create a situation that is unroutable if related logic is not kept together.
  • Although static nets can cross through reconfigurable Pblocks to allow communication between two static islands, it is best to limit this approach, because locked static nets can block routing during subsequent reconfigurable module implementations. Building contiguous regions and minimizing overlap is the best layout strategy for DFX designs.

The Vivado tools determine that two portions of a Pblock are disjoint if the corresponding expanded routing footprint for a collection of resources has a gap between it and another routing footprint section for the same Pblock. The reconfigurable Pblock does not own general routing resources within this gap. This means that finding a solution that connects these disjoint sections is either difficult or impossible, depending on how the Pblock is created. Use hd_visual scripts (e.g., <pblock>_Routing_AllTiles.tcl) to see the routing footprint of a reconfigurable partition Pblock.