Xilinx Virtual Cable (XVC) Flow for Versal Devices - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English

XVC is also supported on AMD Versal™ devices as a software-only solution that runs as an application on the APU under Linux and requires no additional IP. For more information, see the AMDVirtualCable GitHub repository at the following link https://github.com/Xilinx/XilinxVirtualCable.

Note: At the current time, only PL debug cores are supported for use with XVC on Versal devices. Examples of PL debug cores are AXIS-ILA and AXIS-VIO. Versal hard-block debug cores such as SYSMON, DDRMC Calibration Debug, PCI® Express Link Debug and IBERT do not currently support remote access over XVC.