Xilinx Virtual Cable (XVC) - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English

Vivado IDE supports the Xilinx Virtual Cable (XVC) protocol. XVC lets you access and debug an AMD device without using USB or parallel configuration cable. This capability helps facilitate Vivado IDE to debug for designs that:

  • Have the FPGA in a hard-to-access location, where a "lab-PC" is not convenient.
  • Do not have direct access to the device pins on the board - for example, if the JTAG pins are only accessible with a local microprocessor interface.

XVC is an internet-based (TCP/IP) protocol that acts like a JTAG cable. It has very basic cable commands. This allows XVC to debug a system over an intranet, or even the internet. With this capability you can save on costly or impractical travel and reduce the time it takes to debug a remote system.

Another common use of XVC is for shared systems that are not co-located with teams that need access to them. It can also be used when there are physical constraints to using the system, such as when the JTAG connector is not available or accessible. XVC implementation is programming language and platform independent.

Rather than using a dedicated JTAG header, an existing Ethernet connection can be used to create the appropriate JTAG commands from a processor to a target device. With the XVC v1.0 Protocol, Vivado can communicate the same JTAG commands over an Ethernet connection and still support all of the existing Vivado debug features.

Important: If the Vivado Debug Bridge IP is used for XVC, Vivado IDE does not support programming features. The assumption is that the device is programmed before using XVC to debug the design. The Debug Bridge IP is not compatible with Versal adaptive SoC.