An alternative way to program FPGAs and configuration memory devices is using a standard test and programming language (STAPL) file. The STAPL file generated through AMD Vivado™ Design Suite and AMD Vivado™ Lab Edition contains low-level JTAG instructions and data required to program these devices. Once the file is generated, boundary scan test tools can be used independently of the Vivado IDE.
The general steps to create an STAPL file are as follows:
- Create a STAPL target.
- Add devices to the STAPL target.
- Add operations to the devices in the STAPL chain.
- Write STAPL files.
- Close STAPL target.
- (Optional) Execute STAPL.
Step 4 records the program operations sequentially and stored as a cached file. The cached file is written out to a target destination in step 5. After the file is created, it can be used by boundary scan tools or executed through Vivado Design Suite or Vivado Lab Edition tools.