Serial I/O Hardware Debugging Flows - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English
Note: For AMD Versal™ Serial I/O Hardware Debugging Flows, see Versal Serial I/O Hardware Debugging Flows.

The AMD Vivado™ IDE provides a quick and easy way to generate a design that helps you debug and verify your system that uses AMD high-speed gigabit transceiver (GT) technology. The in-system serial I/O debugging flow has three distinct phases:

  1. IBERT Core generation phase: Customizing and generating the IBERT core that best meets your hardware high-speed serial I/O requirements.
  2. IBERT Example Design Generation and Implementation phase: Generating the example design for the IBERT core generated in the previous step.
  3. Serial I/O Analysis phase: Interacting with the IBERT IP contained in the design to debug and verify issues in your high-speed serial I/O links.

The rest of this chapter shows how to complete the first two phases. The third phase is covered in Debugging the Serial I/O Design in Hardware.