Instantiating the Debug Cores - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English

After generating the debug core, instantiate it in your HDL source code and connect it to the signals that you wish to probe for debugging purposes. Following is an example of the ILA instance in a Verilog HDL source file:

Note: Unlike the legacy VIO and ILA v1.x cores, the new ILA core instance does not require a connection to an ICON core instance. Instead, a debug core hub (dbg_hub) is automatically inserted into the synthesized design netlist to provide connectivity between the new ILA core and the JTAG scan chain.