Hardware System Communication Using the JTAG-to-AXI Master Debug Core - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English

The JTAG-to-AXI Master debug core is a customizable core that can generate the AXI transactions and drive the AXI signals internal to an FPGA at runtime. The core supports all memory-mapped AXI and AXI-Lite interfaces and can support 32 or 64-bit wide data interfaces.

The JTAG-to-AXI Master (JTAG-AXI) cores you add to your design appear in the Hardware window under the target device. If you do not see the JTAG-AXI cores appear, right-click the device and select Refresh Hardware. This re-scans the FPGA and refreshes the Hardware window.

Note: If you still do not see the ILA core after programming and/or refreshing the FPGA device, check to make sure the device was programmed with the appropriate .bit file and check to make sure the implemented design contains an ILA core.

Click to select the JTAG-AXI core (called hw_axi_1 in the following figure) to see its properties in the AXI Core Properties window.

Figure 1. JTAG-to-AXI Master Core in the Hardware Window