From PCIe to JTAG - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English

In a PCIe setup, you can use the Debug Bridge in the PCIe to JTAG mode to communicate with the debug cores. In this mode, Debug Bridge connects to the Extended Configuration Interface of the PCIe® IP, which in turn can communicate over JTAG to the debug hub on a different target FPGA.

Figure 1. PCIe® to JTAG Debug Bridge Used with PCIe Extended Configuration Interface