From AXI to JTAG - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
Release Date
2023.2 English

This bridge type is intended for designs that use Xilinx Virtual Cable (XVC) to remotely debug an FPGA or SoC device through Ethernet or other interfaces. In this mode, the Debug Bridge receives XVC commands via AXI4-Lite interface to send over the JTAG pins to a target device. For more information see the Debug Bridge LogiCORE IP Product Guide (PG245).

Figure 1. AXI to JTAG Debug Bridge