Configuration Failures in Master Mode - 2023.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

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2023.2 English
Note: The following is not supported on MPSoC or Versal architectures.

Configuration failures can occur when a board is in Master BPI or Master SPI mode and the JTAG cable is connected to the Vivado Hardware Manager. When the Hardware Manager polling and recover feature interrupts the Master mode configuration, intermittent configuration failures occur on power up. To avoid this issue, set the following parameter in the Vivado Hardware Manager Tcl console to ensure that the configuration status registers are not updated:

set_param xicom.allow_cfgin_commands false
Note: This parameter affects all devices in the chain.