Using the Schematic Window - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

The schematic is a graphical representation of the netlist. View the schematic to:

  • View a graphical representation for the netlist.
  • Review the gates, hierarchies, and connectivity.
  • Trace and expand cones of logic.
  • Analyze the design.
  • Better understand what is happening inside the design.

At the RTL level in Elaborated Design, you see how the tool has interpreted your code. In Synthesize Design and Implemented Design, you see the gates generated by the synthesis tool. To open the schematic, select Tools > Schematic. If nothing is selected, the gates, hierarchy, and connectivity appear at the top level of the design, as shown in the following figure.

Figure 1. Top Level Schematic

Tip: The schematic is simpler if you use a single level of hierarchy only. The schematic populates with the selected element emphasized (blue). The ports for the single hierarchy display.
Figure 2. Schematic with Single Hierarchy Selected

You can trace the schematic in multiple ways:

  • Click the + (plus) icon in the upper left to display the gates in the hierarchy.
  • Double-click a port or element to expand it.
  • Right-click and select Schematic from the popup menu.
  • Click the <- -> navigation arrows to switch between the previous and next schematic views.

For more information about schematics, see this link in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).

After implementation, the schematic is the easiest way to visualize the gates in a timing path. Select the path, then open the schematic with the gates and nets from that path.

Figure 3. Schematic with Timing Path

To identify the relevant levels of hierarchy of a selected cell in the schematic, choose Select Leaf Cell Parents from the popup menu.

Figure 4. Timing Path with Select Primitive Parents

As you review the schematic, select Highlight and Mark commands to track leaf cells of interest. Color coding cells (using either a mark or a highlight) makes it easier to track which logic was in the original path, and which logic was added.

Figure 5. Schematic with Timing Path Marked