Timer Settings Section - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

The Timer Settings section of the Timing Summary Report contains details on the Vivado IDE timing analysis engine settings used to generate the timing information in the report. The following figure shows the default options in an example of the Timer Settings section, which includes:

  • Enable Multi-Corner Analysis: This analysis is enabled for each corner (Multi-Corner Configuration).
  • Enable Pessimism Removal (and Pessimism Removal Resolution): Ensures that the source and destination clocks of each path are reported with no skew at their common node.
    Note: This setting must always be enabled.
  • Enable Input Delay Default Clock: Creates a default null input delay constraint on input ports with no user constraint. It is disabled by default.
  • Enable Preset / Clear Arcs: Enables timing path propagation through asynchronous pins. It does not affect recovery/removal checks and is disabled by default.
  • Disable Flight Delays: Disables package delays for I/O delay calculations.
    Figure 1. Timing Summary Report: Timer Settings

For additional information on default timer settings and how to change them, see config_timing_analysis, available from this link in the Vivado Design Suite Tcl Command Reference Guide (UG835).