TIMING-48: Max Delay Datapath Only Constraint on Latch Input - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

A max delay datapath only constraint has been detected on the input of latch <pin_name> (see constraint position <position> in the Timing Constraint window in the Vivado IDE). This constraint is typically used on asynchronous clock domain crossings and can trigger unrealistic latch time borrowing which impacts the QoR of the downstream timing paths.