TIMING-47: False Path, Asynchronous Clock Group or Max Delay Datapath Only Constraint between Synchronous Clocks - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

A <message_string> timing constraint is set between synchronous clocks <clock_group> and <clock_group> (see the constraint position <message_string> in the Timing Constraint window in the Vivado IDE). Masking entire synchronous clock domains using set_false_path, set_clock_groups, or set_max_delay -datapath_only might result in failure in hardware.