TIMING-38: Bus Skew Constraint Applied on Multiple Clocks - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

Multiple clocks are involved on the source or destination of a bus skew constraint (see constraint position <position> in the Timing Constraint window in the Vivado IDE). It is recommended to have only one source clock and one destination clock per bus skew constraint. The first endpoint covered by the constraint is <object>.