TIMING-31: Multicycle Path on Phase-Shifted Clock - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

The MMCM (or PLL) generated clock <clock_name> is phase shifted and is involved in one or several multicycle path constraints for setup only. Because the MMCM (or PLL) property PHASESHIFT_MODE is set to LATENCY, the legacy multicycle path constraint(s) might no longer be required.