Synthesis Log - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

The Vivado Synthesis Log is the primary output from the Vivado Synthesis tool including:

  • The files processed, which are:
    • VHDL
    • Verilog
    • System Verilog
    • XDC
  • Parameter settings per cell
  • Nets with Multiple Drivers
  • Undriven hierarchical pins
  • Optimization information
  • Black boxes
  • Final Primitive count
  • Cell usage by Hierarchy
  • Runtime and memory usage
    Important: Review this report or the messages tab for Errors, Critical Warnings and Warnings. The Synthesis tool can issue Critical Warnings and Warnings that become more serious later in the flow.