Single-Bit Synchronizer - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID
Release Date
2023.2 English

The simplified topology of a Single-bit synchronizer is shown in the following figure. The ASYNC_REG property must be set on at least the first two flip flops of the synchronization chain. The synchronizer depth is defined by the number of chained flip-flops that share the same control signals.

Figure 1. Simplified Topology of a Single-Bit Synchronizer

If the CLEAR or PRESET pins of the flip-flops are also connected to an asynchronous source, the synchronizer is only reported as a single-bit synchronizer and not as an asynchronous reset synchronizer.