Multi-Clock Fanin - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

In the Multi-Clock Fanin example shown in the following figure, both clk_a and clk_x are transferring data through combinatorial logic (LUT2) to the synchronizer circuit in the clk_b domain. It is recommended to first synchronize the source data from clk_a and clk_x individually before combining them via some interconnect logic | FPGA logic. This improves the MTBF characteristics of the overall CDC structure, and it prevents glitches to propagate to the destination clock domain.

Figure 1. Multi-Clock Fanin Example