Example: Reporting the Timing Exceptions Affecting the Timing Analysis - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

This example describes how to take the design, shown in the following figure, through some timing exceptions. The design is fully constrained (clk and input/output delays defined relative to clk).

Figure 1. Fully Constrained Design for Timing Exception Example

The first mode of operation of the Report Exception command is report_exceptions.

  1. Select Window > Timing Constraints.
  2. In the Timing Constraints window, add the following timing exceptions to the design:
    set_multicycle_path 3 -from [get_cell int10_reg] -to [get_cell int20_reg]
    id="ab439753">set_multicycle_path 4 -to [get_cell int20_reg]
    set_false_path -from [get_ports in6] -to [get_cell int20_reg]
    set_false_path -to [get_ports out5] 
    set_false_path -to [get_cell int21_reg]
    set_false_path -from [get_ports in6] -to [get_ports out6]
    set_max_delay 5 -to [get_ports out6]
    set_min_delay 3 -from [get_cells int10_reg] -to [get_cell int20_reg]

The Timing Constraints window displays the timing constraints applied to the design, as shown in the following figure.

Figure 2. Timing Constraints Window Displaying Timing Constraint Changes

The actual Exception Report (report_exceptions) is shown in the following figure.

Figure 3. Report Exception

The Exceptions Report contains the following information:

  • The Position column indicates the constraint position number. This is the same position number reported by the Timing Constraint window (shown previously).
  • The From/Through/To columns indicate the patterns or objects specified with -*from/-*through/-*to command line options (including all the rise/fall versions of those options). An asterisk is displayed when the associated option was not specified.
  • The Setup/Hold columns indicate whether the constraint applies to setup check, hold check, or both. The naming conventions for the Setup/Hold columns are shown in the following table:
    Table 1. Setup/Hold Column Naming Conventions
    Short Name Timing Exception
    cycles= set_multicycle_path
    false set_false_path
    max= set_max_delay
    max_dpo= set_max_delay -datapath_only
    min= set_min_delay
    clock_group= set_clock_group
  • The Status column reports a message when a constraint is partially overridden by another timing exception. The naming conventions for the Status column are shown in the following table:
    Table 2. Status Column Naming Conventions
    Short Timing Exception
    MCP multicycle path
    FP false path
    MXD max delay
    MND min delay
    CG clock group
    Note: The clock group is only reported in the Status column of the report_timing -ignored command when a clock group constraint overrides another timing exception.

In this example, there are two messages regarding partially overridden constraints:

  • The timing constraint position 5 (set_multicycle_path 4 -to [get_cell int20_reg] based on the Timing Constraints window) is partially overridden by the multicycle constraint position 4 (set_multicycle_path 3 -from [get_cell int10_reg] -to [get_cell int20_reg]) and by the false path constraint position 6 (set_false_path -from [get_ports in6] -to [get_cell int20_reg]).
  • The timing constraint position 10 (set_max_delay 5 -to [get_ports out6]) is partially overridden by the false path position 9 (set_false_path -from [get_ports in6] -to [get_ports out6]).