Example - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

In the following example, two MMCM outputs are used to generate the clocks. The BUFGCE_DIV output has a divisional clock, clk1, which has the master clock coming from CLKOUT0. CLKOUT1 has a generated clock, clk2. If you add a constraint such as set_clock_groups -asynchronous -group [get_clocks clk1] -group [get_clocks clk2], there will be a TIMING-47 warning on it.

Figure 1. False Path, Asynchronous Clock Group, or Max Delay Datapath Only Constraint between Synchronous Clocks

Because both clk1 and clk2 are coming from the same MMCM, they are considered to be synchronous to each other. Data crossing to these domains is also considered to be under the synchronous CDC. There is therefore no need to add set_clock_groups -asynchronous.