Description - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

This check applies to Versal adaptive SoC only.

When the MMCM/XPLL/DPLL is configured with digital deskew, the pin phase shift can only be modeled as a latency delay through the CMB and not as a change in the clock waveform. This clocking element is configured with PHASESHIFT_MODE=WAVEFORM, which cannot be honored by the timer. The violation does not impact the signoff timing accuracy because the tool enforces the latency modeling.