Challenging Timing Paths - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

The Challenging Timing Paths section lists key properties of timing paths that have failed checks in the Assessment Details section. By default, the command evaluates 100 failing paths per clock group. It analyzes the following factors:

  • Net budget
  • LUT budget
  • Clock skew

The following figure shows an example of the Net/LUT budget report.

Figure 1. Net/LUT Budget Report

For these checks, estimated net or LUT delays are replaced with more typical values expected for the device and a new budget is calculated. Other penalties are added to the paths when they start or end at block RAMs, DSPs, or other hard blocks. There are different penalties when it is not possible to leverage clock tree skew to improve margin. The new slack based on the penalized path is shown in the LUT Check Slack and Net Check Slack columns.

Path-related QoR suggestions are shown in the SuggestionsID column. Items where suggestions do not exist should be investigated and potentially recoded. Where suggestions exist, applying the suggestion might resolve the issue without requiring code edits.

The Clock Skew section, shown in the following figure, reports on items relating to the clock skew:

  • Skew value
  • Source and destination clock names
  • Clock root on both source and destination clocks
  • Uncertainty
Figure 2. Clock Skew Report