Category 2: Logic - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English
  • Path: The Start Point Pin Primitive, End Point Pin Primitive, Start Point Pin, End Point Pin, Logic Levels, Logical Path, and Routes provide some basic information about the timing path.
    • The Start Point Pin Primitive and End Point Pin Primitive are the reference pin names of the timing path start point and end point. Check that the Start Point Pin Primitive and End Point Pin Primitive are expected timing path start and endpoints. The Start Point Pin and End Point Pin identify the actual timing path pin startpoints and endpoints that would show in the header of a typical timing report.

    Check for endpoint pins such as CLR, PRE, RST, and CE that could potentially be part of high-fanout nets for control signals such as asynchronous resets and clock enable signals. Also check the type of cell, because some primitives like block RAMs and DSPs have larger Clock-to-Q delay and setup/hold requirements than other cells. Their presence in the path can potentially consume a significant portion of the path timing budget.

    • The Logic Levels and Logical Path detail the number of logic levels and the types of primitives in the datapath. Routes indicates the number of routable nets in the datapath. You can use this information to quickly check if a high number of logic levels is mostly due to LUTs or to a mix of LUT/CARRY/MUXF cells. CARRY and MUXF cells are usually connected to nets with dedicated routes that have null or very small delays, while LUT inputs always need to be routed through the fabric.

    When the path mostly contains LUTs, it is also important to check their size. Try to understand why there are several smaller LUTs (non-LUT6) that are chained and what prevents synthesis from targeting LUT6 only, which can reduce the logic levels. There can be properties like KEEP/DONT_TOUCH/MARK_DEBUG or mid-to-high fanout nets in the path that also impact mapping efficiency.

    Based on the outcome of your analysis, you can either modify the RTL source, add/modify attributes in the RTL, or use different synthesis settings to reduce the number of LUTs on the path. Also, you can use the option -remap of the opt_design command to re-optimize LUT mapping and possibly eliminate some smaller LUTs.

  • Cells: Presence of DSP block(s) and BRAM(s) in the datapath. Timing is more difficult to meet on paths from RAMBs or DSPs with no output registers and with several logic levels. You should consider modifying your design to use the RAMB or DSP output registers if these paths are having difficulty meeting the timing requirements.