CE-Controlled CDC - 2023.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

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2023.2 English

In the CE-controlled CDC example shown in the following figure, the clock enable signal is synchronized in the destination clk_b domain before being used to control the crossing flip-flops.

Figure 1. CE-Controlled CDC Example

The CDC engine only checks that the signal connected to FF3/CE is also launched by clk_b. There is no restriction on how the clock enable signal is synchronized or on the circuitry driving the CE pin, as long as it is separately reported as a safe CDC path. Also, you are responsible for constraining the latency from the clk_a domain to FF3, which is usually done by a set_max_delay -datapath_only constraint.