Timing Constraints - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2023.2 English

Timing constraints must be passed to the synthesis engine by means of one or more XDC files. Only the following constraints related to setup analysis have any real impact on synthesis results:

  • create_clock
  • create_generated_clock
  • set_input_delay
  • set_output_delay
  • set_clock_groups
  • set_false_path
  • set_max_delay
  • set_multicycle_path