RTL Attributes - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

RTL attributes must be written in the RTL files. They usually choose the mapping style of certain part of the logic, preserving certain registers and nets, or controlling the design hierarchy in the final netlist.

For more information, see 'Synthesis Attributes' section in the Vivado Design Suite User Guide: Synthesis (UG901).

Note: The DONT_TOUCH attribute does not obey the properties of USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION. If you use DONT_TOUCH properties in the synthesis XDC, it is propagated to implementation regardless of the value of USED_IN_IMPLEMENTATION.

For more information about USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION, refer to Synthesis and Implementation Constraint Files.

DONT_TOUCH attribute example:

set_property DONT_TOUCH true [get_cells fsm_reg]