Output Delays - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2023.2 English

Similar to the Input delays step, the Timing Constraints wizard analyzes the paths to all output ports to identify their source clocks inside the design and their active edges. The template selection rules are the same as described in Input Delays. The following figure shows several output constraints proposed by the wizard and partially edited by the user.

Figure 1. Recommended Output Delay Constraint Templates

For each constraint, three characteristics can be edited in order specify the appropriate waveform that corresponds to the actual interface timing on the board:

Describes the nature of the clock-data relationship (see Input Delays for more details).
Describes the data transition alignment with respect to the active clock edge.
Use this setting when the template delay parameters are specified based on the data valid window timing characteristics outside the FPGA.
Skew (Source Synchronous only)
Use this setting when the template delay parameters are specified based on the skew requirements on the output pin of the FPGA.
Data Rate and Edge
Describes the active clock edges constrained by the template (see Input Delays for more details).

As with recommended input delay constraints, the reference clock is typically the board clock, except in the following cases:

  • The board clock and the output path internal clock have different clock periods.

    The output constraint references a virtual clock that has the same waveform as the internal clock so that the setup analysis is performed with a 1-cycle path requirement. The virtual clock is automatically created.

  • The output path internal clock has a negative phase-shift compared to the board clock.

    The wizard uses a virtual clock as the reference clock. The virtual clock is automatically created with the same waveform as the board clock. In addition, the wizard also specifies a multicycle path constraint between the virtual clock and the internal clock to adjust the default analysis to 1 period + the amount of phase-shift for setup. The combination of the virtual clock and the multicycle path constraint provides simpler constraints for the Vivado Design Suite timer to handle and can only affect output ports that reference to the virtual clock.

    Note: For a positive phase-shift, the virtual clock and the multicycle path constraint are not needed because the default setup path requirement is 1 cycle minus the amount of phase-shift.
  • A forwarded clock has been identified for timing the output path based on the shared clocking connectivity.

    The forwarded clock must have been created during the third step of the wizard Forwarded Clocks, or else the board clock or a virtual clock is used as the output delay constraint reference clock.

The following figure shows a basic example of an output source synchronous path along with its forwarded clock for the 7 series family. Both ODDR/OSERDES instances are connected to the same clock net (highlighted in blue). The ck_vsf_clk_2 generated clock is already defined on the vsf_clk_2 output port.

Figure 2. Example of a Source Synchronous Output Path with its Forwarded Clock

The following figure shows the corresponding constraints in the wizard.

Figure 3. Recommended Source Synchronous Output Path Delay Constraint with a Forwarded Clock

After you select the proper template, enter the delay parameters values. To accelerate the delay parameter entry task, select and edit several constraints with same clock and same template at once. After the constraints have been completed and applied, review their corresponding Tcl syntax in the Tcl Command Preview tab or click Next to proceed to the next step.

Tip: The Timing Constraints wizard skips output ports with a false path constraint. The false path constraint can only be created outside the wizard.