Input Delay - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2023.2 English

The set_input_delay command specifies the input path delay on an input port relative to a clock edge at the interface of the design.

Video: For training on input delay, see the Vivado Design Suite QuickTake Video: Setting Input Delay.

When considering the application board, the input delay represents the phase difference between:

  1. The data propagating from an external chip through the board to an input package pin of the FPGA, and
  2. The relative reference board clock.

Consequently, the input delay value can be positive or negative, depending on the clock and data relative phase at the interface of the device.

Note: Input delays can also be set on internal data pins such as, STARTUPE3/DATA_IN[0:3] (AMD UltraScale+™ devices).