Example Five: Tracing the Master Clock through Combinational Arcs Only - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

In this example, assume that the master clock drives both a register-based clock divided-by-2 and a clock multiplexer that can select the master clock or the divided-by-2 clock from the register clock divider. In this scenario, there are two paths from the master clock to the generated clock, which are through a sequential arc and through a combinational arc. You want to create a generated clock on the multiplexer output that reflects the latency of the combinational path from the master clock through the multiplexer. This is done by using the -combinational command line option:

create_generated_clock -name clkout -source [get_pins mmcm0/CLKIN] -combinational [get_pins MUX/O]