Disabling Timing Arcs - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

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2023.2 English

You can disable timing arcs inside the cell with the set_disable_timing command. Only timing arcs going from input to output ports of a cell can be disabled.

Note: The set_disable_timing command can also be used to disable a timing arc from a port or a wire. In such cases, the command line options -from and -to are not used and only the port object(s) or timing arc object(s) are specified.

Some timing arcs are automatically disabled by the timer to handle specific cases. For instance, combinational feedback loops are not recommended and cannot be properly timed. The timer breaks such loops by disabling one of the timing arcs inside the loop.

Another example is a case analysis set on a MUX. By default, all the data inputs of a MUX are propagated to the output port but when a case analysis is set on the select signals, only one data input port gets propagated to the output port. This is done by the timer by breaking timing arcs from the other data input ports to the output port.

The set_disable_timing command gives you the ability to manually break cell timing arcs in the design. You can, for example, decide which timing arc(s) of a combinational feedback loop should be disabled to break the loop instead of letting the tool make this determination.

Also, suppose that multiple clocks arrive on a LUT input pins but only one clock should be propagated to the LUT output port. This scenario can be handled by breaking the timing arcs associated to the clocks that should not propagate.

There is also a scenario involving LUTRAM that can be quite frequent. Inside the LUTRAM, there is physical path from WCLK pin to the output O pin between the write and read clocks. However, LUTRAM-base asynchronous FIFO are designed in such way that this CDC path WCLK->O cannot happen by construction. Nevertheless, this timing arc is enabled and can result is the timer reporting paths through this WCLK->O timing arc. This arc can also trigger some TIMING-10 DRC violations. In such case, the user should disable the WCLK->O arc so that those paths are not timed and reported and that they do not trigger invalid DRC violations. This timing arc is automatically disabled in the current implementation of the AMD LUTRAM-based FIFO.

Note: After a timing arc is disabled, no timing path is reported by the timer through this arc. You should be very careful to not disable any valid timing arc. This might result is masking some timing violations and/or timing problems that could result in the design failing in hardware.

The syntax for the set_disable_arc command is:

set_disable_timing [-from <arg>] [-to <arg>] [-quiet] [-verbose] <objects>

Only pin names and not Vivado tools objects can be provided to the -from and -to command line options. The pin names should also match pin names from the library cell, not design pin names. For example:

set_disable_timing -from WCLK -to O [get_cells inst_fifo_gen/ gdm.dm/gpr1.dout_i_reg[*]]

The above command disables the WCLK->O timing arcs for all the LUTRAM-based asynchronous FIFOs inst_fifo_gen/ gdm.dm/gpr1.dout_i_reg[*].

The command line options -from and -to are optional. If -from is not specified, then all the timing arcs ending on the pin specified with -to are being disabled. In the same way if -to is not specified, then all the timing arcs starting on the pin specified with -from are being disabled. If neither -from nor -to are specified, then all the timing arcs of the cells specified in the command are disabled.

You can use the command report_disable_timing to list all the timing arcs that have been automatically disabled by the timer as well as manually disabled by the user. Be careful as the list can be very large. Use the -file command line option to save the result in a file.

Note: report_disable_timing can be scoped to one or more hierarchical module(s) with -cells.