Combinational Delays - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

Some paths propagate directly from input ports to output ports without being captured inside the device by a sequential cell. If an input port is connected to both an output port and a sequential cell, the Timing Constraints wizard does not recommend combinational constraints between the input/output port pair, because the input port should have been constrained during the Input Delay step. For the combinational paths, the wizard recommends to define a virtual clock along with input and output delays on the design ports as shown in the following figure.

Figure 1. Combinational Path Schematics and Delay Constraints

The final combinational path delay constraints are:

  • For setup analysis:

    virtual clock period - max input delay - max output delay

  • For hold analysis:

    0 - min output delay - min input delay

The virtual clock period must be modified so that it is greater than the largest combinational delay constraint across all constrained combinational paths. The following figure shows the delay entries needed per input/output ports pair.

Figure 2. Recommended Combination Paths Constraints

None of the input and output delay constraints override existing ones. If a given port has multiple delay constraints with respect to the same clock, the smallest value of all constraints is used by the Vivado Timing analysis feature during hold analysis, and the largest one during setup analysis.

After all delay entries have been filled, click Next to proceed to the next step.

Note: Alternatively, you can constrain combinational paths using the set_max_delay and set_min_delay commands outside the Timing Constraints wizard.