Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
Release Date
2023.2 English

Set CLOCK_DEDICATED_ROUTE on a net to indicate how the clock signal is expected to be routed.

The CLOCK_DEDICATED_ROUTE property is used on a clock net to override the default routing. This is an advanced control requiring extreme caution as it might affect timing predictability and routability.

For example, CLOCK_DEDICATED_ROUTE can be set to FALSE when dedicated clock routing is not available. A value of FALSE allows the Vivado tools to route the clock from an input port to a global clocking resource such as a BUFG or MMCM using general routing resources. This should only be used as a last resort when device package pin assignments have been locked down, and the clock input cannot be assigned to an appropriate clock capable input pin (CCIO). The routing is suboptimal and unpredictable unless used with FIXED_ROUTE.

For more information about this property, see Clock Constraints in the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).