BEL/LOC Constraints - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

For complex structures, the BEL or LOC constraints may need to be specified in addition to the RLOC. The BEL constraint must be used to align the cells inside the RPM set, for example, to align the LUTs with the registers. The LOC constraint is uncommon and typically not used because the RPM set is forced on a specific site in the device and cannot be moved by the placer. Whenever some BEL or LOC constraints need to be specified, it is important to not mix the source of those constraints. The BEL/LOC constraints should be entirely specified either through RTL or through XDC, but not a combination of both. Following is an example of BEL constraints specified at the RTL.

Verilog file:

(*BEL="H6LUT",RLOC="X0Y0"*) LUT6 S0_LUTH (...); 
(*BEL="G6LUT",RLOC="X0Y0"*) LUT6 S0_LUTG (...); 
(*BEL="F6LUT",RLOC="X0Y0"*) LUT4 S0_LUTF (...); 
(*BEL="E5LUT",RLOC="X0Y0"*) LUT4 S0_LUTE (...); 
(*BEL="D6LUT",RLOC="X0Y0"*) LUT6 S0_LUTD (...); 
(*BEL="C6LUT",RLOC="X0Y0"*) LUT6 S0_LUTC (...); 
(*BEL="B6LUT",RLOC="X0Y0"*) LUT4 S0_LUTB (...); 
(*BEL="A5LUT",RLOC="X0Y0"*) LUT4 S0_LUTA (...);

(*BEL="CARRY8",RLOC="X0Y0"*) CARRY8#(.CARRY_TYPE("DUAL_CY4")) S0_CARRY8(...);
 
(*BEL="HFF2",RLOC="X0Y0"*) FD FD_out5 (...);
(*BEL="GFF2",RLOC="X0Y0"*) FD FD_out4 (...);
(*BEL="FFF2",RLOC="X0Y0"*) FD FD_out3 (...);
(*BEL="DFF2",RLOC="X0Y0"*) FD FD_out2 (...);
(*BEL="CFF2",RLOC="X0Y0"*) FD FD_out1 (...);
(*BEL="BFF2",RLOC="X0Y0"*) FD FD_out0 (...);
Note: The INIT string has been omitted for simplification.

In the following example, the RPM is defined at the RTL but the BEL constraints are specified through XDC.

Verilog file:

(*RLOC="X0Y0"*) LUT6 S0_LUTH (...);
(*RLOC="X0Y0"*) LUT6 S0_LUTG (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTF (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTE (...);
(*RLOC="X0Y0"*) LUT6 S0_LUTD (...);
(*RLOC="X0Y0"*) LUT6 S0_LUTC (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTB (...);
(*RLOC="X0Y0"*) LUT4 S0_LUTA (...);

(*RLOC="X0Y0"*) CARRY8#(.CARRY_TYPE("DUAL_CY4")) S0_CARRY8(...);
 
(*RLOC="X0Y0"*) FD FD_out5 (...);
(*RLOC="X0Y0"*) FD FD_out4 (...);
(*RLOC="X0Y0"*) FD FD_out3 (...);
(*RLOC="X0Y0"*) FD FD_out2 (...);
(*RLOC="X0Y0"*) FD FD_out1 (...);
(*RLOC="X0Y0"*) FD FD_out0 (...);
Note: The INIT string has been omitted for simplification.

XDC file:

set_property BEL CARRY8 [get_cells S0_CARRY8] 
set_property BEL HFF2 [get_cells FD_out5] 
set_property BEL GFF2 [get_cells FD_out4] 
set_property BEL FFF2 [get_cells FD_out3] 
set_property BEL DFF2 [get_cells FD_out2] 
set_property BEL CFF2 [get_cells FD_out1] 
set_property BEL BFF2 [get_cells FD_out0] 
set_property BEL A5LUT [get_cells S0_LUTA] 
set_property BEL B6LUT [get_cells S0_LUTB] 
set_property BEL C6LUT [get_cells S0_LUTC] 
set_property BEL D6LUT [get_cells S0_LUTD] 
set_property BEL E5LUT [get_cells S0_LUTE]
set_property BEL F6LUT [get_cells S0_LUTF] 
set_property BEL G6LUT [get_cells S0_LUTG] 
set_property BEL H6LUT [get_cells S0_LUTH]