Automatically Derived Clocks - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

Automatically derived clocks are also called auto-generated clocks. The Vivado IDE automatically creates the constraint for these on the output pins of the Clock Modifying Blocks (CMBs), provided the associated master clock has already been defined.

In the AMD 7 series device family, the CMBs are:

  • MMCM*/ PLL*
  • BUFR
  • PHASER*

In the AMD UltraScaleā„¢ device family, the CMBs are:

  • MMCM* / PLL*
  • BUFG_GT / BUFGCE_DIV
  • GT*_COMMON / GT*_CHANNEL / IBUFDS_GTE3
  • BITSLICE_CONTROL / RX*_BITSLICE
  • ISERDESE3

An auto-generated clock is not created if a user-defined clock (primary or generated) is also defined on the same netlist object, that is, on the same definition point (net or pin). The auto-derived clock is named with the segment name in the top-most hierarchy of the net that is connected to the definition point.