About Timing Exceptions - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

A timing exception is needed when the logic behaves in a way that is not timed correctly by default. You must use a timing exception command any time you want the timing handled differently (for example, for logic that only has the result captured every other clock cycle by design).

The AMD Vivado™ IDE supports the timing exceptions commands shown in the following table:

Table 1. Timing Exceptions Commands
Command Function
set_multicycle_path Indicates the number of clock cycles required to propagate data from the start to the end of a path.
set_false_path Indicates that a logic path in the design should not be analyzed.
set_max_delay set_min_delay Sets the minimum and maximum path delay value. This overrides the default setup and hold constraints with user specified maximum and minimum delay values.
Note: For runtime consideration, Vivado tools do not provide on-the-fly analysis for conflicting timing exceptions. Run report_exceptions for full analysis and reporting of the timing exceptions. For more information, refer to Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).