About Constraining I/O Delay - 2023.2 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2023-11-01
Version
2023.2 English

To accurately model the external timing context in your design, you must give timing information for the input and output ports. Because the AMD Vivado™ Integrated Design Environment (IDE) recognizes timing only within the boundaries of the FPGA, you must use the following commands to specify delay values that exist beyond these boundaries:

  • set_input_delay
  • set_output_delay