The Vivado IDE times the paths between all
the clocks in your design by default, unless you specify otherwise by using clock groups
or false path constraints. The set_clock_groups
command
disables timing analysis between groups of clocks that you identify, and not between the
clocks within the same group. Unlike with the set_false_path
constraint, timing is ignored on both directions between
the clocks.
Multiple groups of clocks can be specified using the -group
option
multiple times. If none of the clocks in a group exist in the design, the group becomes
empty. The set_clock_groups
constraint stays valid only when at least
two groups are valid and not empty. If only one group remains valid and all the other
groups are empty, then the set_clock_groups
constraint is not applied
and an error message is generated.
Use the schematic viewer or the clock networks report to visualize the topology of the clock trees, and determine which clocks must not be timed together. You can also use the clock interactions report to review the existing constraints between two clocks, and determine whether they share the same primary clock, specifically if they have a known phase relationship or identify the clocks with no common period (unexpandable).